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[ DevCourseWeb.com ] Udemy - Verilog HDL programming with practical approach

  • ~Get Your Files Here !/17 - Project 3 Hamming code complete Design & TB for error detection & correction/001 Hamming code complete Design & TB for error detection & correction.mp4 224.1 MB
  • ~Get Your Files Here !/02 - Introduction to Verilog HDL/001 Verilog fundamentals.mp4 173.6 MB
  • ~Get Your Files Here !/16 - Project 2 FIFO/008 Verilog HDL code for FIFO Test Bench.mp4 155.0 MB
  • ~Get Your Files Here !/18 - FPGA/001 FPGA.mp4 138.1 MB
  • ~Get Your Files Here !/13 - FSM/001 FSM ( Finite State Machine) & Hardware modeling of FSM, Example Verilog code.mp4 132.5 MB
  • ~Get Your Files Here !/15 - Project 1 Memory controller/001 Memory controller with Design & TB.mp4 97.3 MB
  • ~Get Your Files Here !/16 - Project 2 FIFO/007 Verilog HDL for FIFO design.mp4 93.8 MB
  • ~Get Your Files Here !/01 - Introduction to the course/002 Sample program on edaplayground.mp4 92.1 MB
  • ~Get Your Files Here !/01 - Introduction to the course/001 Preview.mp4 88.7 MB
  • ~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/002 FPGA vs ASIC.mp4 84.0 MB
  • ~Get Your Files Here !/03 - VLSI design flow ( FPGA & ASIC)/001 VLSI Design flow (FPGA & ASIC).mp4 80.3 MB
  • ~Get Your Files Here !/12 - Functions & Task and system tasks/002 File based system tasks and random generator system task.mp4 71.8 MB
  • ~Get Your Files Here !/09 - Behavioral Modeling/001 Behavioral Modeling - Introduction.mp4 70.2 MB
  • ~Get Your Files Here !/14 - Sequence detector using FSM with complete Design & TB/001 Sequence detector using FSM with complete Design & TB.mp4 68.2 MB
  • ~Get Your Files Here !/09 - Behavioral Modeling/005 Assignment Statements - Blocking & Non-blocking.mp4 66.3 MB
  • ~Get Your Files Here !/11 - Test bench/002 Example - Test bench for counter design.mp4 65.4 MB
  • ~Get Your Files Here !/16 - Project 2 FIFO/009 Run the simulation and finding errors and Analyze the waveform Results.mp4 64.2 MB
  • ~Get Your Files Here !/09 - Behavioral Modeling/003 Procedural Blocks- initial & always.mp4 64.0 MB
  • ~Get Your Files Here !/11 - Test bench/003 Example - Test bench for Pulse generator.mp4 61.1 MB
  • ~Get Your Files Here !/12 - Functions & Task and system tasks/001 Functions & tasks and system tasks.mp4 52.1 MB
[磁力链接] 添加时间:2022-05-01 大小:3.0 GB 最近下载:2025-06-13 热度:1621

[ DevCourseWeb.com ] Udemy - Communication Series P1 - Uart, Spi And I2C In Verilog

  • ~Get Your Files Here !/3 - I2C/74 - I2C Master without clock stretch.mp4 193.7 MB
  • ~Get Your Files Here !/1 - UART/15 - UART 16550 TX LCR Line Control Register.mp4 94.3 MB
  • ~Get Your Files Here !/1 - UART/26 - UART 16550 Registers THR and RBR.mp4 92.8 MB
  • ~Get Your Files Here !/3 - I2C/78 - I2C Slave without clock stretch.mp4 91.9 MB
  • ~Get Your Files Here !/1 - UART/1 - Simple UART TX.mp4 84.0 MB
  • ~Get Your Files Here !/2 - SPI/47 - Understanding CPOL behavior.mp4 79.5 MB
  • ~Get Your Files Here !/1 - UART/21 - UART 16550 RX RX Logic.mp4 76.4 MB
  • ~Get Your Files Here !/2 - SPI/57 - Digilent PMOD DA4 Analog Devices AD5628 Understanding Specifications.mp4 66.6 MB
  • ~Get Your Files Here !/1 - UART/34 - TX testbench.mp4 65.9 MB
  • ~Get Your Files Here !/3 - I2C/82 - Bit Banging.mp4 59.0 MB
  • ~Get Your Files Here !/1 - UART/17 - UART 16550 TX TX Logic.mp4 52.1 MB
  • ~Get Your Files Here !/3 - I2C/79 - Testbench for top.mp4 51.7 MB
  • ~Get Your Files Here !/1 - UART/14 - TUART 16550 TX Understanding Oversampling in Baud Generator.mp4 50.1 MB
  • ~Get Your Files Here !/1 - UART/16 - UART 16550 TX Stop bits.mp4 49.2 MB
  • ~Get Your Files Here !/1 - UART/29 - UART 16550 Registers LSR.mp4 47.9 MB
  • ~Get Your Files Here !/1 - UART/22 - UART 16550 RX RX TB.mp4 47.9 MB
  • ~Get Your Files Here !/1 - UART/18 - UART 16550 TX TX TB.mp4 47.0 MB
  • ~Get Your Files Here !/1 - UART/28 - UART 16550 Registers FCR and LCR.mp4 46.3 MB
  • ~Get Your Files Here !/1 - UART/3 - Simple UART TB.mp4 43.0 MB
  • ~Get Your Files Here !/1 - UART/8 - UART 16550 FIFO P2.mp4 42.7 MB
[磁力链接] 添加时间:2024-01-27 大小:2.3 GB 最近下载:2025-06-09 热度:2473

[ FreeCourseWeb.com ] Udemy - Digital Design using Verilog HDL programming with practical.zip

  • [ FreeCourseWeb.com ] Udemy - Digital Design using Verilog HDL programming with practical.zip 1.7 GB
[磁力链接] 添加时间:2021-04-19 大小:1.7 GB 最近下载:2025-06-09 热度:1157

[ FreeCourseWeb.com ] Udemy - Verilog Quick Revision and FAQs.zip

  • [ FreeCourseWeb.com ] Udemy - Verilog Quick Revision and FAQs.zip 229.1 MB
[磁力链接] 添加时间:2021-04-10 大小:229.1 MB 最近下载:2025-06-07 热度:102

verilog视频课程（特权和红色飓风）

  • Lesson06：Quartus.II使用简介与第一个工程实例.(ED2000.COM).wmv 212.6 MB
  • Lesson02：可编程逻辑器件基础.(ED2000.COM).wmv 191.0 MB
  • Lesson10：BJ-EPM240学习板实验3——Johnson.计数器实验.(ED2000.COM).wmv 189.3 MB
  • Lesson14：BJ-EPM240学习板实验7——串口通信实验.(ED2000.COM).wmv 182.8 MB
  • Lesson33：SF-EP1C开发板实验10——基于SDRAM读写的串口调试实验.(ED2000.COM).wmv 173.9 MB
  • Lesson32：如何使用TimeQuest.(ED2000.COM).wmv 168.5 MB
  • Lesson04：Verilog语法基础.(ED2000.COM).wmv 147.7 MB
  • Lesson23：SF-EP1C开发板实验2——基于74HC595的数码管实验.(ED2000.COM).wmv 147.2 MB
  • Lesson16：BJ-EPM240学习板实验9——I2C通信实验.(ED2000.COM).wmv 139.2 MB
  • Lesson07：BJ-EPM240学习板实验1——分频计数实验.(ED2000.COM).wmv 138.2 MB
  • Lesson22：SF-EP1C开发板实验1——AS和JTAG配置方式.(ED2000.COM).wmv 135.5 MB
  • Lesson28：SF-EP1C开发板实验7——基于M4K块的单口RAM配置仿真实验.(ED2000.COM).wmv 119.0 MB
  • Lesson05：BJ-EPM240学习板介绍.(ED2000.COM).wmv 115.4 MB
  • Lesson18：BJ-EPM240学习板实验11——MAX.II内部震荡时钟使用实例.(ED2000.COM).wmv 115.0 MB
  • Lesson09：BJ-EPM240学习板实验2——按键消抖实验.(ED2000.COM).wmv 114.6 MB
  • Lesson17：BJ-EPM240学习板实验10——SRAM读写实验.(ED2000.COM).wmv 114.0 MB
  • Lesson15：BJ-EPM240学习板实验8——PS2键盘解码实验.(ED2000.COM).wmv 111.0 MB
  • Lesson13：BJ-EPM240学习板实验6——VGA接口实验.(ED2000.COM).wmv 110.7 MB
  • Lesson35：SF-EP1C开发板实验12——DIY数码相框.(ED2000.COM).wmv 106.7 MB
  • Lesson31：时序分析基础.(ED2000.COM).wmv 104.0 MB
[磁力链接] 添加时间:2025-05-21 大小:4.7 GB 最近下载:2025-05-22 热度:5


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