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[ DevCourseWeb.com ] Udemy - Simple Axi Bus Design Using Verilog Hdl

  • ~Get Your Files Here !/4 - Source code/14 - Design of AXI bus using verilog HDL write process.mp4 292.9 MB
  • ~Get Your Files Here !/4 - Source code/15 - Design of AXI bus using verilog HDL Read process.mp4 129.3 MB
  • ~Get Your Files Here !/1 - Course Introduction/1 - Introduction.mp4 23.6 MB
  • ~Get Your Files Here !/2 - AXI bus/8 - Signal Diagram.mp4 20.9 MB
  • ~Get Your Files Here !/4 - Source code/17 - Test bench simulation.mp4 19.9 MB
  • ~Get Your Files Here !/2 - AXI bus/5 - AXI channel Architecture of Readwrites.mp4 18.4 MB
  • ~Get Your Files Here !/2 - AXI bus/10 - Read process Timing diagram.mp4 15.8 MB
  • ~Get Your Files Here !/1 - Course Introduction/3 - Comparision between AHB AXI APB.mp4 13.5 MB
  • ~Get Your Files Here !/4 - Source code/16 - AXI master slave.mp4 13.4 MB
  • ~Get Your Files Here !/2 - AXI bus/9 - Write process Timing diagram.mp4 12.7 MB
  • ~Get Your Files Here !/2 - AXI bus/6 - AXI signals.mp4 12.6 MB
  • ~Get Your Files Here !/2 - AXI bus/7 - Handshaking signals.mp4 12.5 MB
  • ~Get Your Files Here !/3 - Implementation of Simple AXI bus/13 - AXI MasterSlave Block diagram and Writeread process.mp4 11.6 MB
  • ~Get Your Files Here !/2 - AXI bus/11 - Dependencies between channel handshake signals.mp4 11.5 MB
  • ~Get Your Files Here !/1 - Course Introduction/2 - AMBA introduction.mp4 6.6 MB
  • ~Get Your Files Here !/2 - AXI bus/4 - Introduction to AXI.mp4 6.4 MB
  • ~Get Your Files Here !/3 - Implementation of Simple AXI bus/12 - AXI state machine for write read.mp4 2.5 MB
  • ~Get Your Files Here !/4 - Source code/14 - axi-master-write.v 3.2 kB
  • ~Get Your Files Here !/4 - Source code/14 - axi-slave-write.v 2.7 kB
  • ~Get Your Files Here !/4 - Source code/15 - axi-master-read.v 2.6 kB
[磁力链接] 添加时间:2024-02-15 大小:624.1 MB 最近下载:2025-06-15 热度:1541

[ DevCourseWeb.com ] Udemy - RTL Finite State Machines in System Verilog

  • ~Get Your Files Here !/5 - RTL FSM - Fewer States/3 -Fewer States.mp4 33.9 MB
  • ~Get Your Files Here !/5 - RTL FSM - Fewer States/1 -Measure Latency - 1.mp4 32.8 MB
  • ~Get Your Files Here !/4 - RTL FSM Example/6 -Synthesis.mp4 29.3 MB
  • ~Get Your Files Here !/9 - EDA Playground Setup (Optional)/1 -EDA Playground Hints (Optional).mp4 27.6 MB
  • ~Get Your Files Here !/5 - RTL FSM - Fewer States/2 -Measure Latency - 2.mp4 27.3 MB
  • ~Get Your Files Here !/6 - Extra Explicit One Hot Encoding/2 -GCDOne Hot Encoded.mp4 26.7 MB
  • ~Get Your Files Here !/4 - RTL FSM Example/5 -RTL Simulation - 2.mp4 24.8 MB
  • ~Get Your Files Here !/4 - RTL FSM Example/2 -State Definitions.mp4 21.9 MB
  • ~Get Your Files Here !/4 - RTL FSM Example/4 -RTL Simulation - 1.mp4 20.1 MB
  • ~Get Your Files Here !/4 - RTL FSM Example/3 -Transition Arcs.mp4 17.7 MB
  • ~Get Your Files Here !/8 - Docker Setup (Optional)/1 -Docker Windows Install (Optional).mp4 14.7 MB
  • ~Get Your Files Here !/7 - Wrap Up/1 -Wrap Up.mp4 14.0 MB
  • ~Get Your Files Here !/6 - Extra Explicit One Hot Encoding/5 -Gatesim.mp4 13.6 MB
  • ~Get Your Files Here !/1 - Welcome to the course !/3 -FSMs in Digital Logic.mp4 11.9 MB
  • ~Get Your Files Here !/1 - Welcome to the course !/1 -Introduction.mp4 10.7 MB
  • ~Get Your Files Here !/5 - RTL FSM - Fewer States/4 -Synthesis.mp4 10.2 MB
  • ~Get Your Files Here !/3 - RTL FSM Design Pattern/1 -RTL FSM Design Pattern.mp4 9.2 MB
  • ~Get Your Files Here !/6 - Extra Explicit One Hot Encoding/1 -One-Hot Encoding.mp4 9.0 MB
  • ~Get Your Files Here !/8 - Docker Setup (Optional)/4 -Test Install.mp4 8.0 MB
  • ~Get Your Files Here !/8 - Docker Setup (Optional)/2 -Download Docker Image.mp4 7.5 MB
[磁力链接] 添加时间:2024-10-27 大小:401.2 MB 最近下载:2025-06-16 热度:1534

[ FreeCourseWeb.com ] Udemy - Verilog Interview Preparation Guide.zip

  • [ FreeCourseWeb.com ] Udemy - Verilog Interview Preparation Guide.zip 229.1 MB
[磁力链接] 添加时间:2024-12-07 大小:229.1 MB 最近下载:2025-06-16 热度:871

[ DevCourseWeb.com ] Udemy - Hands-on development of cpu- soc on FPGA using vhdl(verilog)

  • ~Get Your Files Here !/18 -888.mp4 461.5 MB
  • ~Get Your Files Here !/14 -how to control memory operation, register operation, alu operation etc.mp4 304.8 MB
  • ~Get Your Files Here !/6 -Extracting instruction set from RISC-V datasheet.mp4 261.9 MB
  • ~Get Your Files Here !/8 -how to setup the read and write register alias table.mp4 203.3 MB
  • ~Get Your Files Here !/7 -introducing the counter-track out-of-order execution.mp4 176.0 MB
  • ~Get Your Files Here !/17 -the cache control.mp4 171.0 MB
  • ~Get Your Files Here !/16 -how to setup the cache control for hit, miss, cache address and memory address.mp4 150.4 MB
  • ~Get Your Files Here !/15 -how control handles cache misses and cache hit.mp4 128.1 MB
  • ~Get Your Files Here !/13 -how to connect different units using the control.mp4 127.9 MB
  • ~Get Your Files Here !/19 -top wiring and conclusion.mp4 110.6 MB
  • ~Get Your Files Here !/3 -accessing resource file.mp4 110.4 MB
  • ~Get Your Files Here !/9 -feedback how to return registers after instruction exec using output buffers.mp4 101.4 MB
  • ~Get Your Files Here !/5 -how to link program memory to instruction buffer and program counter buffer.mp4 86.8 MB
  • ~Get Your Files Here !/11 -architecture of a register bank.mp4 72.5 MB
  • ~Get Your Files Here !/12 -how to handle multiple function units. introducing memory buffers.mp4 54.7 MB
  • ~Get Your Files Here !/10 -How to design a simple ALU.mp4 49.2 MB
  • ~Get Your Files Here !/2 -Architecture of the design.mp4 47.9 MB
  • ~Get Your Files Here !/4 -How to design the program memory.mp4 39.5 MB
  • ~Get Your Files Here !/1 -Introduction.mp4 21.2 MB
  • ~Get Your Files Here !/3 -class_resources.zip 11.6 MB
[磁力链接] 添加时间:2025-02-13 大小:2.7 GB 最近下载:2025-06-16 热度:1341

verilog视频课程（特权和红色飓风）

  • Lesson06：Quartus.II使用简介与第一个工程实例.(ED2000.COM).wmv 212.6 MB
  • Lesson02：可编程逻辑器件基础.(ED2000.COM).wmv 191.0 MB
  • Lesson10：BJ-EPM240学习板实验3——Johnson.计数器实验.(ED2000.COM).wmv 189.3 MB
  • Lesson14：BJ-EPM240学习板实验7——串口通信实验.(ED2000.COM).wmv 182.8 MB
  • Lesson33：SF-EP1C开发板实验10——基于SDRAM读写的串口调试实验.(ED2000.COM).wmv 173.9 MB
  • Lesson32：如何使用TimeQuest.(ED2000.COM).wmv 168.5 MB
  • Lesson04：Verilog语法基础.(ED2000.COM).wmv 147.7 MB
  • Lesson23：SF-EP1C开发板实验2——基于74HC595的数码管实验.(ED2000.COM).wmv 147.2 MB
  • Lesson16：BJ-EPM240学习板实验9——I2C通信实验.(ED2000.COM).wmv 139.2 MB
  • Lesson07：BJ-EPM240学习板实验1——分频计数实验.(ED2000.COM).wmv 138.2 MB
  • Lesson22：SF-EP1C开发板实验1——AS和JTAG配置方式.(ED2000.COM).wmv 135.5 MB
  • Lesson28：SF-EP1C开发板实验7——基于M4K块的单口RAM配置仿真实验.(ED2000.COM).wmv 119.0 MB
  • Lesson05：BJ-EPM240学习板介绍.(ED2000.COM).wmv 115.4 MB
  • Lesson18：BJ-EPM240学习板实验11——MAX.II内部震荡时钟使用实例.(ED2000.COM).wmv 115.0 MB
  • Lesson09：BJ-EPM240学习板实验2——按键消抖实验.(ED2000.COM).wmv 114.6 MB
  • Lesson17：BJ-EPM240学习板实验10——SRAM读写实验.(ED2000.COM).wmv 114.0 MB
  • Lesson15：BJ-EPM240学习板实验8——PS2键盘解码实验.(ED2000.COM).wmv 111.0 MB
  • Lesson13：BJ-EPM240学习板实验6——VGA接口实验.(ED2000.COM).wmv 110.7 MB
  • Lesson35：SF-EP1C开发板实验12——DIY数码相框.(ED2000.COM).wmv 106.7 MB
  • Lesson31：时序分析基础.(ED2000.COM).wmv 104.0 MB
[磁力链接] 添加时间:2025-05-21 大小:4.7 GB 最近下载:2025-05-22 热度:5


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